Course Number & Title:
ENGR 250, "Digital Logic Design" , 5 Credits
"4 hours of lecture and 3 hours of lab (Open Lab Schedule)"
Instructor:
Staff
Text Books:
Digital Logic Design by Khormaee (Link to pdf)
Digital Design by Wakerly (Optional)
Additional Materials:
Link to Canvas
An engineering or scientific calculator such as TI-89
USB thumb drive
Prerequisites:
ENGR 120 or CSE 120
COURSE DESCRIPTION & OUTCOMES:
This is the first course in Digital Design's 2-course sequence. This course covers digital design fundamentals and design of digital logic circuits.
Course Outcomes |
Assessments |
Program Outcomes |
1. Formulate solutions to engineering problems using systematic design methodology |
Homeworks, Labs |
AST2-C |
2. Demonstrate understanding of logic families and digital design |
Homeworks, Labs & Tests |
AST2- C |
3. Understand how to document and analyze design data through EDA software tools |
Labs |
AST2-B |
4. Build, test and troubleshoot digital circuits with logic devices and electronics test equipment |
Homeworks, Labs & Tests |
AST2-B & C |
5. Implement and optimize logic functions using Boolean Algebra and Karnaugh Maps |
Homeworks, Labs & Tests |
AST2-B |
6. Design and implement logic circuits to solve practical problems (Sequential/Combinational and Synchronous/Asynchronous) |
Homeworks, Labs & Tests |
AST2-B & C |
7. Understand SSI/MSI/LSI logic systems and their applications |
Homeworks, Labs & Tests |
AST2-B |
8. Recognize timing/triggering faults and utilize latches/flip-flops to minimize them |
Labs |
AST2-B |
9. Practice effective report writing, presentation skills, teamwork and project development skills |
Labs & Project |
Foundation |
TENTATIVE COURSE OUTLINE:
Lecture Topics
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Assignments/Evaluations
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Ch 1. Number Systems, Representations and Codes
- Digital vs. Analog
- Digital Design Overview
- Design Methodologies
- Number Systems (Binary, Octol, Decimal, Hexadecimal)
- Base Conversions
- Binary Arithmetic
- Binary Code
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Ch 2. Boolean Algebra, Functions and Minimization
- Logic Gates
- Boolean Algebra Postulates & Theorems
- Boolean Functions and Canonical Forms
- Function Minimization
- Algebraic and Karnaugh Map (K-Map) Simplification
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Ch 3. Analyzing/Designing Combinational Logic Circuits
- Standard Logic and Schematic Layout
- Designing Logic Circuits
- Compressing Truth Tables & K-map
- Glitches & Their Causes
- Type of Functions and Delays
- Beyond Standard Logic ( Encoders, PLDs, ...)
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Ch 4. Introduction to Feedback Circuits and
Sequential Logic Analysis
- SR Flip-Flops
- Asynchronous Sequential Logic Issues
- Finite State Machines (FSM)
- Additional Flip-Flop Circuits
- Sequential Circuit Analysis
- De-bouncing Switches
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Ch 5. Sequential Circuit Design
and Techniques
- Synchronous Finite State Machine Design
- State Assignment Encoding and Control
- Alternate Finite State Machine Design
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Ch 6. FSM Optimization and Testing
- Review FSM Design Process
- FSM Minimization Using Implication Table
- Design for Testability - Linear Feedback Shift Register, In-circuit Tester and Scan Test.
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Ch 7. Verilog HDL
- History and Steps in HDL Design
- Syntax
- Declarations
- Flow Control
- Modularization
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Ch 8. VHDL
- History and Steps in HDL Design
- Syntax
- Declarations
- Flow Control
- Modularization
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Ch 9. Commercial Digital Integrated Circuits
- Output Types
- Logic Families
- XOR Properties and Applications
- Encoders and Decoders(MUX/DeMUX)
- Adder, Subtractor & Multiplier Design
- Multiplier Design
- Arithmetic Logic Unit (ALU)
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Comprehensive Final Exam - for schedule visit: www.clark.edu/academics/schedule |
ASSESSMENT:
- Quizzes (20 points each)
Each quiz consists of a homework problem and a problem to be solved in-class.
- Midterm test (100 points)
- Comprehensive final exam (150 points)
- Labs Planning, Execution and Reports (20 points each lab)
Each student is expected to complete the weekly lab assignments during lab time. Even though some labs may be performed as a group, the report is to be completed individually, and due on the following lab period.
Note: In order to be eligible to receive a passing grade for the course, all labs must be completed and turned in prior to final exam date.
Students are encouraged to participate in course-related service learning such as club activities and special projects. Attend ECS Club meetings for more information.
ENGINEERING & COMPUTER SCIENCE COURSE POLICIES:
Visit ECS Course Policies for additional important and supporting materials.
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